Design of Voltage Regulator

Example –1

The following data apply to a voltage regulator circuit shown in fig. 1 Unregulated input: Vi = 15 to 20V Desired output: VO = 10V Load current requirements: IO = 0 to 0.1 A Zener diode voltage = 6.8V hFE min = 15 hFE max = 50 Both transistors are the silicon planer type with negligible ICBO. Determine Extreme values of RL Maximum value of IB1 Suitable value for R1 Extreme values of I1 Value of R2 if D1 requires a minimum of 5 mA Worst-case power dissipation for Q1 under normal operating conditions Worst-case power dissipation for Q2 under normal operating conditions

Fig. 1

Solution

(a). Since R_L = V_O / I_O, we can write

The maximum load current is zero; therefore the load resistance is anywhere from 100Ω to an open circuit.

(b). The base current of Q₁ is I_E1 (h_FE1 + 1), where I_E1 is the sum of load current I_O, current through the sampling network, and current through R₂. Usually I_O is the largest component involved; therefore

(c). R₁ should supply the maximum current required by the base of Q₁. This is 6.66 mA; however, it is a good practice to increase it by about 50 percent to provide a safety margin. We therefore select R₁ on the basis that its current must never drop below 10 mA:

(d). The extreme values of I₁ are determined using the extreme values of V_i:

(e).        

(f). Worst-case power dissipation for Q₁ occurs when both the voltage and current are maximum. Normally the collector-base junction dissipates the most power, since its voltage is much greater than V_BE; however, the total transistor dissipation involves both junctions. This can be approximated as follows:

Voltage across Q₁: V_CE1 = V_i – V_O
Current through Q₁: I_C1 ≈ I_E1 ≈ I_O
P_E1 ≈ (V_i – V_O) (I_O)
P_D1≈ (20 – 10) (0.1) = 1 W

(g). Q₂ does not handle large currents as Q₁ does; therefore its power dissipation is relatively low:

P_D2 = (V_CE2) (I_C2)

Both V_A and V_r are relatively constant; therefore V_CE2 is also constant:

V_CE2 = V_A – V_r = V_O + V_EB1 – V_r
V_CE2 = 10 + 0.6 – 6.8 = 3.8 V

The maximum value of I_C2 is approximately equal to I₁ = 21.4 mA; we, therefore, have

P_D2 ≈ V_CE2 I_C2
P_D2 ≈ 4(21.4 x 10^-3) = 81.5 mW

Note that the current through R₁ in this example does not remain constant; in fact, it can vary between 10 and 21.4 mA, a total range of 11.4 mA. The regulator would perform much better if I₁ were regulated.

Example –2

Determine R1 and extreme values of I1 in the circuit of Example-1, if Q 1 is replaced with the compound connection of fig. 2. Assume both transistors have a minimum hFE of 15 and negligible cutoff currents. Solution: The current through R1 should be selected about 50 percent higher than the maximum current required by the base of Q12. For worst-case design, the minimum hFE of 15 is used, yielding a composite hFE ≈ 15 (15) = 225 for both Q11 and Q12. This yields

Fig. 2

We now select I₂≈ 0.65 mA; R₁ is calculated as follows:

where, 

The extreme values of I₁ occurs when V_i is at its extremes. The minimum I₁ is  0.65mA (as indicated above), while the maximum is

The variation in I₁ is 1.5 - 0.65 = 0.85mA.

Example - 3

In the regulator shown in fig. 3 R₁ = 50KΩ, R₂ = 43.75KΩ and V_Z = 6.3V. If the 15 V output drops 0.1 V, find the change in V_BE2 that results.

Fig. 3

Solution:

When V_O = 15 V,

Therefore, V_BE2 = V₂ - V_Z = 7 V - 6.3 V = 0.7 V. When V_O = 15 V - 0.1 V = 14.9 V, V₂ becomes

Therefore,